CD4042 belongs to 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4042 has Quad Clocked D Latch
CD4042 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.
CD4042 Features
- Wide supply voltage range 3.0V to 15V
- High noise immunity 0.45 VDD (typ.)
- Low power TTL Fan out of 2 driving 74L
- compatibility or 1 driving 74LS
- Clock polarity control
- Fully buffered data inputs
- Q and Q outputs
CD4042 Specifications
Absolute Maximum Ratings
- DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
- Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
- Storage Temperature Range (TSTG): -65oC to +150oC
- Lead Temperature (During Soldering): +260oC
CD4042 Pinout Diagram
CD4042 Pin Description
| Pin No | Pin Name | Description |
| 1 | Q4 | D Latch Output 4 |
| 2 | Q1 | D Latch Output 1 |
| 3 | Q1′ | Invert D Latch Output 1 |
| 4 | D1 | D Latch Input 1 |
| 5 | CLK | Clock Pin |
| 6 | POLARITY | Polarity Pin |
| 7 | D2 | D Latch Input 2 |
| 8 | VSS | Supply Voltage |
| 9 | Q2′ | Invert D Latch Output 2 |
| 10 | Q2 | D Latch Output 2 |
| 11 | Q3′ | Invert D Latch Output 3 |
| 12 | Q3 | D Latch Output 3 |
| 13 | D3 | D Latch Input 3 |
| 14 | D4 | D Latch Input 4 |
| 15 | Q4′ | Invert D Latch Output 4 |
| 16 | VDD | Drain Voltage |
CD4042 Circuit
Applications
- used as input / output ports.
CD4042 Alternative Equivalent
Download CD4042 Quad Clocked D Latch Datasheet from the link given below.
