LC78626E Datasheet – Digital Signal Processor IC

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Overview

The LC78626E is a monolithic compact disk player signal processing and servo control CMOS IC equipped with an internal anti-shock control function. Designed for total functionality including support for EFM-PLL, one-bit D/A converter, and containing an analog low-pass filter, the LC78626E provides optimal cost-performance for low-end CD players that provide anti-shock systems.

The basic functions provided by this IC include modulation of the EFM signal from the optical pick-up, deinterleaving, detection, and correction of signal errors, prevention of a maximum of approximately 10 seconds of skipping, signal processing such as digital filtering (which is useful in reducing the cost of the player), and processing of a variety of servo-related commands from the microprocessor.

Part NumberLC78626E
FunctionDigital Signal Processor for Compact Disc Player
PackageQIP100E, FLP100 Type
ManufacturerSANYO (Panasonic)
DatasheetDownload PDF AM5890S pdf

LC78626E Features

  • 100-pin QFP
  • A single 3.2 V/5 V power supply
  • When an HF signal is input, it is sliced to precise levels and converted to an EFM signal. The phase is compared with the internal VCO and a PLL clock is reproduced at an average frequency of 4.3218 MHz.
  • Precise timing for a variety of required internal timing needs (including the generation of the reference clock) is produced by the attachment of an external 16.9344 MHz crystal oscillator.
  • The speed of revolution of the disk motor is controlled by the frame phase difference signal generated by the playback clock and the reference clock.

LC78626E Absolute Maximum Ratings at Ta = 25°C, VSS = 0V

ParameterSymbolRatingsUnit
Maximum power supply voltageVDD maxVSS–0.3 to VSS+7.0V
Input voltageVINVSS–0.3 to VDD+0.3V
Output voltageVOUTVSS–0.3 to VDD+0.3V
Allowable power dissipationPd max400mW
Operating temperature rangeTopr–20 to +75°C
Storage temperature rangeTstg–40 to +125°C

LC78626E Pinout

Pin Definitions

Pin No.Pin NameI/ODescription
1DEFIIDefect detection signal (DEF) input. When not used, must be connected to 0 V.
2TAIIFor the PLLTest input. Equipped with internal pull-down resistor. Must be connected to 0V.
3PDOOExternal VCO control phase comparator output.
4VVSSPInternal VCO ground. Must be connected to 0 V.
5ISETAIPDO output current adjustment resistor connection.
6VVDDPInternal VCO power supply.
7FRAIVCO frequency range adjustment
8VSSPDigital system ground. Must be connected to 0 V.
9TESCLKITest clock input. Must be connected to VDD.
10TESAITest operation mode control input. Must be connected to VDD.
11TESBITest operation mode control input. Must be connected to VDD.
12TESCITest operation mode control input. Must be connected to VDD.
13TESGBITest operation mode control input. Must be connected to VDD.
14TEST5IChip select input. Equipped with an internal pull-down resistor. When not controlled, must be connected to 0 V.
15  CSIFor slice-level control.
16TEST1ITest input. Must be connected to 0 V.
17EFMOOTest input. Equipped with an internal pull-down resistor. Must be connected to 0 V.EFM signal output.
18EFMIIEFM signal input.
19TEST2ISync signal detects output. A high level when the sync signal detected from the EFM signal matches the internally generated sync signal.
20CLV+O  Disk motor control output. Can have a 3-state output depending on the command.
21CLVO
22  V/PORough servo/phase control automatic switching monitor output. If a high level then rough servo mode. If a low level then phase control mode.
23HFLITrack detect signal input. Schmidt input.
24TESITracking error signal input. Schmidt input.
25TOFFOTracking off output.
26TGLOTracking gain switch output. Gain is increased with low level.
27JP+O  Track jump control output. Can be 3-state output depending on the command.
28JPO
29PCKOEFM data playback clock monitor. 4.3218 MHz during phase lock.
30FSEQOSync signal detect output. A high level when the sync signal detected from the EFM signal matches the internally generated sync signal.
31VDDPDigital system power supply.
      32      ASRES      I(I/O)Reset signal input for initializing only the anti-shock control part (i.e. excluding the DSP part). Resets when this pin is low level, and release the reset when this pin is high level. Tie this pin to the low level (i.e., connected to 0 V) if when using software control on the anti-shock part alone through the anti-shock part only reset disable/release command ($F4) or the anti-shock only reset enable/inrush command ($F5). Note: This pin is assigned as the least significant bit of the general I/O port however, use as a general I/O pin is disabled. When the port I/O set command ($DB) is executed, the least significant bit is always “0,” and the output driver is not turned ON.
33CONT2I/OGeneral I/O pin 2. This controls the commands from the microcontroller. When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.
Pin No.Pin NameI/ODescription
  34  CONT3/SBCK  I/OGeneral I/O pin 3. This controls the commands from the microcontroller. This pin is shared exclusively with the subcode read clock input (SBCK). When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.
  35  CONT4/SFSY  I/OGeneral I/O pin 4. This controls the commands from the microcontroller. This pin is shared exclusively with the subcode frame sync signal output (SFSY). When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.
  36  CONT5/PW  I/OGeneral I/O pin 5. This controls the commands from the microcontroller. This pin is shared, exclusively, with the subcode P, Q, R, S, T, U, V, W output (PW). When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.
37SBSYOSubcode block sync signal output.
38TEST3ITest input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
39DOUTODigital output. EIAJ format.
40TEST4ITest input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
4116MO16.9344 MHz output.
424.2MO4.2336 MHz output.
43EFLGODRAM switch: high: 1M, low : 4M
44FSXO7.35 kHz sync signal output (frequency divided from the crystal oscillator).
45EMPHODeemphasis monitor output. When high level, a deemphasis disk is being played back.
46C2FOC2 flag output.
47TOUTOTest output. Under normal operation, this should be left open.
48MR1IOperating mode switch: high: shockproof, low: through.
49TESEITest input. Must be connected to 0V.
50TESDITest input. Must be connected to 0V.
51MUTESLO      For the one-bit D/A converterL channel mute output.
52LVDDPL channel power supply.
53LCHOAOL channel output.
54L/RVSSPL/R channel ground. Must be connected to 0 V.
55RCHOAOR channel output.
56RVDDPR channel power supply.
57MUTEROR channel mute output.
58XVDDPCrystal oscillator power supply.
59XOUTO  16.9344 MHz crystal oscillator connection.
60XINI
61XVSSPCrystal oscillator ground. Must be connected to 0 V.
62RWCIRead/write control input. Schmidt input.
63COINIMicrocontroller command input.
64  CQCKIInput pin for the command input latch clock and the subcode readout clock. Schmitt input.
65SQOUTOSubcode Q output.
66WRQOSubcode Q output standby output.
67FMTIOperating mode switch: high: shock proof, low: through.
68EMPPODRAM empty (an RZP pulse is output when the DRAM is empty).
69 RESIExternal reset input: low reset (all internal blocks are reinitialized).
Pin No.Pin NameI/ODescription
70MMC0ORemaining DRAM output.
71MMC1ORemaining DRAM output.
72MMC2ORemaining DRAM output.
73MMC3ORemaining DRAM output.
74OVFODRAM write terminated. (An RZP pulse is output when there is an overflow or a shock.)
75CNTOKOC2F shock detects pause signal input: low: pause shock detection.
76WOKIDRAM write enable signal input: high: write enable.
77PAUSE INIPause signal input: high: pause.
78NGJOC2F data contact point detection start signal: low ® high: detection start.
79EMPNORemaining DRAM alarm output: low: memory low.
80SHOCKIC2F shock detect pause signal input: low: pause shock detection.
81DRAM3I/ODRAM data bus
82DRAM2I/ODRAM data bus
83DRAM1I/ODRAM data bus
84DRAM0I/ODRAM data bus
85  OEODRAM control signal.
86  WEODRAM control signal.
87  CASODRAM control signal.
88  RASODRAM control signal.
89AD9ODRAM address bus
90AD8ODRAM address bus
91AD7ODRAM address bus
92AD6ODRAM address bus
93AD5ODRAM address bus
94VSSPDigital system ground. Must be connected to 0 V.
95AD4ODRAM address bus
96AD3ODRAM address bus
97AD2ODRAM address bus
98AD1ODRAM address bus
99AD0ODRAM address bus
100VDDPDigital system power supply.

Applications

  • Audio processing IC
  • Digital sound controller
  • Home entertainment systems
  • Hi-fi audio devices

LC78626E Datasheet

Download the LC78626E IC Datasheet from the link given below.