74LS107 Dual J-K Flip-Flop with Clear


The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. 74LS107 contains two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The 74LS107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-the-low clock must be stable while the clock is in high transition.

74LS107 Features

  • Dual JK Flip Flop Package IC
  • -ve edge triggered
  • Operating Voltage (Nom): 5V
  • Frequency at normal voltage (Max): 35MHz
  • Propagation delay (Max): 20ns
  • IOL (Max): 8mA
  • IOH (Max):-0.4mA

74LS107 Specifications

Supply Voltage4.75 – 5.25Vdc
Maximum Clock Frequency40Mhz
Power Dissipation2mW/gate @100kHz
Minimum Output Current8mA
Propagation Delay10nS
Fan Out (TTL Loads)20

74LS107 Pinout Diagram

74LS107 Pin Description

Pin NoPin NameDescription
1J1Input Pin J1
2Q1′Active low output pin 1
3Q1Active high Output pin 1
4K1Input Pin K1
5Q2Active high Output pin 2
6Q2′Active low output pin 2
8J2Input Pin J2
9CP2Clock Pulse Input Pin 2
10CD2Digital Clock Pin 2
11K2Input Pin K2
12CP1Clock Pulse Input Pin 1
13CD1Digital Clock Pin 1
14VCCPositive Supply


  • Event Detectors
  • Data Synchronizers
  • Frequency Divider

74LS107 Alternative Equivalent

74LS109, 74LS112

Download 74LS107 Dual J-K Flip-Flop with Clear Datasheet from the link given below.