The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. 74LS107 contains two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The 74LS107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-the-low clock must be stable while the clock is in high transition.
74LS107 Features
- Dual JK Flip Flop Package IC
- -ve edge triggered
- Operating Voltage (Nom): 5V
- Frequency at normal voltage (Max): 35MHz
- Propagation delay (Max): 20ns
- IOL (Max): 8mA
- IOH (Max):-0.4mA
74LS107 Specifications
| Supply Voltage | 4.75 – 5.25Vdc |
| Maximum Clock Frequency | 40Mhz |
| Power Dissipation | 2mW/gate @100kHz |
| Minimum Output Current | 8mA |
| Propagation Delay | 10nS |
| Fan Out (TTL Loads) | 20 |
74LS107 Pinout Diagram
74LS107 Pin Description
| Pin No | Pin Name | Description |
| 1 | J1 | Input Pin J1 |
| 2 | Q1′ | Active low output pin 1 |
| 3 | Q1 | Active high Output pin 1 |
| 4 | K1 | Input Pin K1 |
| 5 | Q2 | Active high Output pin 2 |
| 6 | Q2′ | Active low output pin 2 |
| 7 | GND | Ground |
| 8 | J2 | Input Pin J2 |
| 9 | CP2 | Clock Pulse Input Pin 2 |
| 10 | CD2 | Digital Clock Pin 2 |
| 11 | K2 | Input Pin K2 |
| 12 | CP1 | Clock Pulse Input Pin 1 |
| 13 | CD1 | Digital Clock Pin 1 |
| 14 | VCC | Positive Supply |
Applications
- Event Detectors
- Data Synchronizers
- Frequency Divider
74LS107 Alternative Equivalent
74LS109, 74LS112
Download 74LS107 Dual J-K Flip-Flop with Clear Datasheet from the link given below.
