74LS112 Dual J-K Negative Edge-triggered Flip-Flop


The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. 74LS112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs set or resets the outputs regardless of the levels of the other inputs.

74LS112 Features

  • Two Independent JK Negative Edge Triggered Flip-Flops
  • Separate Preset and Clear Inputs
  • Fast Switching Times
  • Operating Temperature up to 70°C
  • Standard TTL Switching Voltages

74LS112 Specifications

Supply Voltage4.75 – 5.25Vdc
Maximum Clock Frequency40Mhz
Power Dissipation2mW/gate @100kHz
Minimum Output Current8mA
Propagation Delay10nS
Fan Out (TTL Loads)20

74LS112 Pinout Diagram

74LS112 Pin Description

Pin NoPin NameDescription
1CPClear/Clock Pin
2K1Data Input Pin K1
3J1Data Input Pin J1
4SDSerial Data Pin
5Q1′Output Active Low Pin Q1′
6Q1Output Active High Pin Q1
7Q2Output Active High Pin Q2
9Q2′Output Active Low Pin Q2′
10SDSerial Data Pin
11J2Data Input Pin J2
12K2Data Input Pin K2
13CPClear/Clock Pin
14CD1Digital Clock Pin 1
15CD2Digital Clock Pin 2
16VCCPositive Supply

74LS112 Circuit


  • Event Detectors
  • Data Synchronizers
  • Frequency Divider

74LS112 Alternative Equivalent

74LS107, 74LS109

Download 74LS112 Dual J-K Negative Edge-triggered Flip-Flop Datasheet from the link given below.