74LS114-Dual JK Negative Edge Flip Flop

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The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. 74LS114 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs set or resets the outputs regardless of the levels of the other inputs.

74LS114 Features

  • Fully Buffered to Offer Maximum Isolation from External Disturbance

74LS114 Specifications

Supply Voltage4.75 – 5.25Vdc
Maximum Clock Frequency40Mhz
Power Dissipation2mW/gate @100kHz
Minimum Output Current8mA
Propagation Delay10nS
Fan Out (TTL Loads)20

74LS114 Pinout Diagram

74LS114 Pin Description

Pin NoPin NameDescription
1CDDigital Clock Pin
2K1Data Input Pin K1
3J1Data Input Pin J1
4SDSerial Data Pin
5Q1Output Active High Pin Q1
6Q1′Output Active Low Pin Q1′
7GNDGround
8Q2Output Active High Pin Q2
9Q2′Output Active Low Pin Q2′
10SDSerial Data Pin
11J2Data Input Pin J2
12K2Data Input Pin K2
13CPClear/Clock Pin
14VCCPositive Supply

74LS114 Circuit

Here is a simple circuit of JK Flip Flop using logic gate NAND

Applications

  • Event Detectors
  • Data Synchronizers

74LS114 Alternative Equivalent

74LS112

Download 74LS114-Dual JK Negative Edge Flip Flop Datasheet from the link given below.