The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. The 74LS279 offers 4 basic S-R flip-flop latches in one 16-pin, 300-mil package. Under conventional operation, the S-R inputs are normally held high. When the S input is pulsed low, the output will be set high. When R I pulsed low, the Q output will be reset low.
74LS279 Features
- Four Individual and Independent Set-Reset Latches
- Inputs Voltage Level Triggered
- Fast Propagation Times
- Operating Temperature up to 70°C
- Standard TTL Switching Voltages
74LS279 Specifications
| Supply Voltage | 4.75 – 5.25Vdc |
| Maximum Clock Frequency | 40Mhz |
| Power Dissipation | 2mW/gate @100kHz |
| Minimum Output Current | 8mA |
| Propagation Delay | 10nS |
| Fan Out (TTL Loads) | 20 |
74LS279 Pinout Diagram
74LS279 Pin Description
| Pin No | Pin Name | Description |
| 1 | R | Reset Pin |
| 2 | S1 | Set Pin 1 Of Latch 1 |
| 3 | S2 | Set Pin 2 Of Latch 1 |
| 4 | Q | Output Of Latch 1 |
| 5 | R | Reset Pin |
| 6 | S1 | Set Pin 1 Of Latch 2 |
| 7 | Q | Output Of Latch 2 |
| 8 | GND | Ground Pin |
| 9 | Q | Output Of Latch 3 |
| 10 | R’ | Reset Pin(Active Low) |
| 11 | S’2 | Set Pin(Active Low) of Latch 3 |
| 12 | S’1 | Set Pin(Active Low) of Latch 3 |
| 13 | Q | Output Of Latch 4 |
| 14 | R’ | Reset Pin(Active Low) |
| 15 | S’1 | Set Pin(Active Low) of Latch 4 |
| 14 | VCC | Positive Supply |
Applications
- As the latch is a single-bit storage element, it may be used as a storage device in power gating circuits and clock.
- They may be used as pulse latches where they perform the same behavior as flip-flops by pulsing the clock very quickly.
74LS279 Alternative Equivalent
Download the 74LS279 Quad Set-Reset Latches Datasheet from the link given below.
