The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. 74LS73 Dual JK Flip-Flop with Clear contains two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The 107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices, the J and K inputs must be stable while the clock is high.
74LS73 Features
- Two Independent Negative Edge Triggered JK Flip-Flops
- Clear Input Resets the Output
- Fast Switching Times
- Operating Temperature up to 70°C
- Standard TTL Switching Voltages
74LS73 Specifications
| Supply Voltage | 4.75 – 5.25Vdc |
| Maximum Clock Frequency | 40Mhz |
| Power Dissipation | 2mW/gate @100kHz |
| Minimum Output Current | 8mA |
| Propagation Delay | 10nS |
| Fan Out (TTL Loads) | 20 |
74LS73 Pinout Diagram
74LS73 Pin Description
| Pin No | Pin Name | Description |
| 1 | CP | Clock Pin |
| 2 | CD | Clear Pin |
| 3 | K | Data Input K |
| 4 | VCC | Positive Supply |
| 5 | CP | Clock Pin |
| 6 | CD | Clear Pin |
| 7 | J | Data Input J |
| 8 | Q2′ | Invert Output Pin 2 |
| 9 | Q2 | Output Pin 2 |
| 10 | K | Data Input K |
| 11 | GND | Ground |
| 12 | Q1 | Output Pin 1 |
| 13 | Q1′ | Invert Output Pin 1 |
| 14 | J | Data Input J |
74LS73 Circuit
Applications
- Event Detectors
- Data Synchronizers
- Frequency Divider
74LS73 Alternative Equivalent
74LS76, 74LS107
Download 74LS73 Dual JK Flip-Flop with Clear Datasheet from the link given below.
