74LS73 Dual JK Flip-Flop with Clear


The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. 74LS73 Dual JK Flip-Flop with Clear contains two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The 107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices, the J and K inputs must be stable while the clock is high.

74LS73 Dual-JK-Flip-Flop-with-Clear-IC

74LS73 Features

  • Two Independent Negative Edge Triggered JK Flip-Flops
  • Clear Input Resets the Output
  • Fast Switching Times
  • Operating Temperature up to 70°C
  • Standard TTL Switching Voltages

74LS73 Specifications

Supply Voltage4.75 – 5.25Vdc
Maximum Clock Frequency40Mhz
Power Dissipation2mW/gate @100kHz
Minimum Output Current8mA
Propagation Delay10nS
Fan Out (TTL Loads)20

74LS73 Pinout Diagram

74LS73 Pin Description

Pin NoPin NameDescription
1CPClock Pin
2CDClear Pin
3KData Input K
4VCCPositive Supply
5CP Clock Pin
6CD Clear Pin
7J Data Input J
8Q2′Invert Output Pin 2
9Q2 Output Pin 2
10K Data Input K
12Q1 Output Pin 1
13Q1′Invert Output Pin 1
14J Data Input J

74LS73 Circuit


  • Event Detectors
  • Data Synchronizers
  • Frequency Divider

74LS73 Alternative Equivalent

74LS76, 74LS107

Download 74LS73 Dual JK Flip-Flop with Clear Datasheet from the link given below.