74LS76 Dual JK Flip-Flop with Preset and Clear


The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. The 74LS76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs.

The 74LS76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices, the J and K inputs must be stable while the clock is high.

74LS76 Features

  • Two Individual Flip-Flops with J,K Clock, Set and Clear Inputs
  • Input Data is Transferred to the Outputs on HIGH-LOW Clock Transition
  • Fast Switching Speed
  • Operating Temperature up to 70°C
  • Standard TTL Switching Voltages

74LS76 Specifications

Supply Voltage4.75 – 5.25Vdc
Maximum Clock Frequency40Mhz
Power Dissipation2mW/gate @100kHz
Minimum Output Current8mA
Propagation Delay10nS
Fan Out (TTL Loads)20

74LS76 Pinout Diagram

74LS76 Pin Description

Pin NoPin NameDescription
1CLK 1Clock Pin 1
2PRE’ 1Invert Preset Pin 1
3CLR’ 1Invert Clear Pin 1
4J1Data Input J1
5VCCSupply Voltage
6CLK 2Clock Pin 2
7PRE’ 2Invert Preset Pin 2
8CLR’ 2Invert Clear Pin 2
9J2Data Input J2
102Q’Invert Output Pin 2Q’
112QOutput Pin 2Q
122KData Input 2K
13GNDGround Pin
141Q’Invert Output Pin 1Q’
151Q Output Pin 1Q
161KData Input 1K

74LS76 Circuit

Here is a simple circuit of J-K Flip Flop with Clock Pin using Logic Gate NAND.


  • Event Detectors
  • Data Synchronizers
  • Frequency Divider

74LS76 Alternative Equivalent

74LS73, 74LS107

Download 74LS76 Dual JK Flip-Flop with Preset and Clear Datasheet from the link given below.