CD40102 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD40102 has Presettable 2-decade BCD down counter
CD40102 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.
CD40102 Features
- High Voltage Type (20V Rating)
- CD40102BMS: 2-Decade BCD Type
- Synchronous or Asynchronous Preset
- Medium Speed Operation
- fCL = 3.6MHz (Typ) at 10V
- Cascadable
- 100% Tested for Maximum Quiescent Current at 20V
- 5V, 10V, and 15V Parametric Ratings
- Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
- Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
CD40102 Specifications
Absolute Maximum Ratings
- DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
- Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
- DC Input Current, Any One Input: ±10mA
- Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
- Storage Temperature Range (TSTG): -65oC to +150oC
- Lead Temperature (During Soldering): +265oC
- At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
CD40102 Pinout Diagram
CD40102 Pin Description
| Pin No | Pin Name | Description |
| 1 | CLK | Clock Pin |
| 2 | CLEAR’ | Invert Clear Pin |
| 3 | (CARRY-IN)’/(COUNTER ENABLE)’ | Invert Carry-input Pin |
| 4 | J0 | Output Bit 1 Of Counter |
| 5 | J1 | Output Bit 2 Of Counter |
| 6 | J2 | Output Bit 3 Of Counter |
| 7 | J3 | Output Bit 4 Of Counter |
| 8 | VSS | Supply Voltage |
| 9 | (ASYNC: PRESET ENABLE)’ | Invert Asynchronous Preset Enable Pin |
| 10 | J4 | Output Bit 5 Of Counter |
| 11 | J5 | Output Bit 6 Of Counter |
| 12 | J6 | Output Bit 7 Of Counter |
| 13 | J7 | Output Bit 8 Of Counter |
| 14 | (ZERO DETECT)’ | Invert Zero Detect Pin |
| 15 | (SYNC: PRESET ENABLE)’/(CARRY-OUT)’ | Invert synchronous Preset Enable Pin |
| 16 | VDD | Drain Voltage |
CD40102 Circuit
Applications
- Divide-By- “N” Counters
- Programmable Times
- Interrupt Timers
- Cycle/Program Counter
CD40102 Alternative Equivalent
Download CD40102-Presettable 2-decade BCD down counter Datasheet from the link given below.
