CD40105 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD40105 has a 4-bit x 16 word FIFO register
CD40105 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.

CD40105 Features
- Independent Asynchronous Inputs and Outputs
- Expandable in Either Direction
- Reset Capability
- Status Indicators on Inputs and Outputs
- Three-State Outputs
- Shift-Out Independent of Three-State Control
CD40105 Specifications
Absolute Maximum Ratings
- DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
- Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
- DC Input Current, Any One Input: ±10mA
- Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
- Storage Temperature Range (TSTG): -65oC to +150oC
- Lead Temperature (During Soldering): +265oC
- At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
CD40105 Pinout Diagram

CD40105 Pin Description
Pin No | Pin Name | Description |
1 | (3-STATE CONTROL)’ | Invert Three-State Control Pin |
2 | DIR | Data Input Ready |
3 | SI | Shift In Pin |
4 | D0 | Data Input Pin 1 |
5 | D1 | Data Input Pin 2 |
6 | D2 | Data Input Pin 3 |
7 | D3 | Data Input Pin 4 |
8 | GND | Ground Pin |
9 | MR | Master Reset Pin |
10 | Q3 | Output 4 |
11 | Q2 | Output 3 |
12 | Q1 | Output 2 |
13 | Q0 | Output 1 |
14 | DOR | Data Output Ready |
15 | SO’ | Invert shift Output |
16 | VCC | Drain Voltage |
CD40105 Circuit
Applications
- Bit-Rate Smoothing
- CPU/Terminal Buffering
- Data Communications
- Peripheral Buffering
- Line Printer Input Buffers
- Auto-Dialers
- CRT Buffer Memories
- Radar Data Acquisition
CD40105 Alternative Equivalent
Download CD40105-4-bit x 16 word FIFO register Datasheet from the link given below.