CD4046 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4046 has Micropower Phase-locked Loop
CD4046 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.

CD4046 Features
- Wide supply voltage range: 3.0V to 18V
- Low dynamic power consumption: 70 µW (typ.) at fo = 10 kHz, VDD = 5V
- VCO frequency: 1.3 MHz (typ.) at VDD = 10V
- Low frequency drift: 0.06%/°C at VDD = 10V with temperature
- High VCO linearity: 1% (typ.)
CD4046 Specifications
Absolute Maximum Ratings
- DC Supply Voltage Range, (VDD): -0.5V to +18V (Voltage Referenced to VSS Terminals)
- Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
- Storage Temperature Range (TSTG): -65oC to +150oC
- Lead Temperature (During Soldering): +260oC
- Power Dissipation (PD)
- Dual-In-Line 700 mW
- Small Outline 500 mW
CD4046 Pinout Diagram

CD4046 Pin Description
Pin No | Pin Name | Description |
1 | PHASE Pulses | Phase Pulses Pin |
2 | PHASE COMP 1 OUT | Phase Comparator 1 Output |
3 | COMPARATOR IN | Comparator Input Pin |
4 | VCO OUT | Output Voltage |
5 | INHIBIT | Inhibit Pin |
6 | C1A | Capacitor 1A |
7 | C1B | Capacitor 1B |
8 | VSS | Supply Voltage |
9 | VCO IN | Input Voltage |
10 | DEMODULATOR OUT | Demodulator Output |
11 | R1 | Resistor 1 |
12 | R2 | Resistor 2 |
13 | PHASE COMP 2 OUT | Phase Comparator 2 Output |
14 | SIGNAL IN | Signal Input Pin |
15 | ZENER | Zener Pin |
16 | VDD | Drain Voltage |
CD4046 Circuit
Applications
- FM demodulator and modulator
- Frequency synthesis and multiplication
- Frequency discrimination
- Data synchronization and conditioning
- Voltage-to-frequency conversion
- Tone decoding
- FSK modulation
- Motor speed contro
CD4046 Alternative Equivalent
Download CD4046 Micropower Phase-locked Loop Datasheet from the link given below.