CD4096-Gated J-K flip-flop (inverting and non-inverting)


CD4096 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4096 has a Gated J-K flip-flop (inverting and non-inverting)

CD4096 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.

CD4096 Features

  • Set-Reset Capability
  • High Voltage Types (20V Rating)
  • CD4095BMS Non-Inverting J and K Inputs
  • CD4096BMS Inverting and Non-Inverting J and K Inputs
  • 16MHz Toggle Rate (Typ.) at VDD – VSS = 10V
  • Gated Inputs
  • Standard Symmetrical Output Characteristics
  • 100% Tested for Maximum Quiescent Current at 20V
  • 5V, 10V, and 15V Parametric Ratings
  • Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
  • Noise Margin (Over Full Package Temperature Range):
    • 1V at VDD = 5V
    • 2V at VDD = 10V
    • 2.5V at VDD = 15V

CD4096 Specifications

Absolute Maximum Ratings

  • DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
  • Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
  • DC Input Current, Any One Input: ±10mA
  • Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
  • Storage Temperature Range (TSTG): -65oC to +150oC
  • Lead Temperature (During Soldering): +265oC
    • At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum

CD4096 Pinout Diagram

CD4096 Pin Description

Pin NoPin NameDescription
1NCNot Connected
2RESETReset Pin
3J1Input Pin J1
4J2 Input Pin J2
5J3′Invert Input Pin J3
6Q’Invert Output
7VSSSupply Voltage
8QOutput Pin
9K3′ Invert Input Pin K3
10K2 Input Pin K2
11K1 Input Pin K1
12CLKClock Pin
13SETSet Pin
14VDDDrain Voltage

CD4096 Circuit


  • Registers
  • Counters
  • Control Circuits

CD4096 Alternative Equivalent


Download CD4096-Gated J-K flip-flop (inverting and non-inverting) Datasheet from the link given below.