CD4526 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4526 has Divide-by-N Counter
CD4526 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.
CD4526 Features
- supply Voltage Range = 3.0 Vdc to 18 Vdc
- Logic Edge−Clocked Design: Incremented on Positive Transition of Clock or Negative Transition of Inhibit
- Asynchronous Preset Enable
- Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range
CD4526 Specifications
Absolute Maximum Ratings
- DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
- Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
- DC Input Current, Any One Input: ±10mA
- Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
- Storage Temperature Range (TSTG): -65oC to +150oC
- Lead Temperature (During Soldering): +265oC
- At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
CD4526 Pinout Diagram
CD4526 Pin Description
| Pin No | Pin Name | Description |
| 1 | Q3 | Counter Output 4 |
| 2 | P3 | Preset Data Input 4 |
| 3 | PE | Preset Enable Pin |
| 4 | INHIBIT | Inhibit Pin |
| 5 | P0 | Preset Data Input 1 |
| 6 | CLK | Clock Pin |
| 7 | Q0 | Counter Output 1 |
| 8 | VSS | Supply Voltage |
| 9 | Q1 | Counter Output 2 |
| 10 | RESET | Reset Pin |
| 11 | P1 | Preset Data Input 2 |
| 12 | “0” | Output Pin |
| 13 | CF | Cascade Feedback |
| 14 | P2 | Preset Data Input 3 |
| 15 | Q2 | Counter Output 3 |
| 16 | VDD | Drain Voltage |
CD4526 Circuit
Applications
- Frequency counters
- Digital clocks
- Analog to digital convertors
CD4526 Alternative Equivalent
CD4059, CD4522
Download CD4526 Divide-by-N Counter Datasheet from the link given below.
