CD4724 belongs to 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4724 has an 8-bit addressable latch
CD4724 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.
CD4724 Features
- High-Voltage Types (20V Rating)
- Storage register capability
- Can function as demultiplexer
- Standard Symmetrical Output Characteristics
- 100% Tested for Maximum Quiescent Current at 20V
- 5V, 10V, and 15V Parametric Ratings
- Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
- Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
CD4724 Specifications
Absolute Maximum Ratings
- DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
- Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
- DC Input Current, Any One Input: ±10mA
- Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
- Storage Temperature Range (TSTG): -65oC to +150oC
- Lead Temperature (During Soldering): +265oC
- At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
CD4724 Pinout Diagram
CD4724 Pin Description
Pin No | Pin Name | Description |
1 | A0 | Input 1 Of Latch |
2 | A1 | Input 2 Of Latch |
3 | A2 | Input 3 Of Latch |
4 | Q0 | Output 1 Of Latch |
5 | Q1 | Output 2 Of Latch |
6 | Q2 | Output 3 Of Latch |
7 | Q3 | Output 4 Of Latch |
8 | VSS | Supply Voltage |
9 | Q4 | Output 5 Of Latch |
10 | Q5 | Output 6 Of Latch |
11 | Q6 | Output 7 Of Latch |
12 | Q7 | Output 8 Of Latch |
13 | DATA | Data Pin |
14 | WRITE DISABLE | Write Disable Pin |
15 | RESET | Reset Pin |
16 | VDD | Drain Voltage |
CD4724 Circuit
Applications
- Multiple line decoders
- A/D converters
CD4724 Alternative Equivalent
CD4099
Download CD4724-8-bit addressable latch Datasheet from the link given below.