N80C196KC20 Datasheet – CHMOS Microcontroller IC



The 80C196KC 16-bit microcontroller is a high-performance member of the MCS 96 microcontroller family. The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation, and an optional 16 Kbytes of ROM/OTPROM. Intel’s CHMOS III process provides a high-performance processor along with low power consumption.

The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16 Kbytes factory-programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise stated.

Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform generation. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or up/down counter.

Part NumberN80C196KC20
FunctionCommercial CHMOS Microcontroller. ROMless, 20MHz
PackagePLCC 68 Pin type
Manufacturer Intel
DatasheetDownload PDF AM5890S pdf

N80C196KC20 Features

  • 16 and 20 MHz Available
  • 488 Byte Register RAM
  • Register-to-Register Architecture
  • 28 Interrupt Sources/16 Vectors
  • Peripheral Transaction Server
  • 1.4 ms 16 x 16 Multiply (20 MHz)
  • 2.4 ms 32/16 Divide (20 MHz)
  • Powerdown and Idle Modes
  • Five 8-Bit I/O Ports
  • 16-Bit Watchdog Timer
  • Extended Temperature Available
  • Dynamically Configurable 8-Bit or 16-Bit Buswidth
  • Full Duplex Serial Port
  • High-Speed I/O Subsystem
  • 16-Bit Timer
  • 16-Bit Up/Down Counter with Capture
  • 3 Pulse-Width-Modulated Outputs
  • Four 16-Bit Software Timers
  • 8- or 10-Bit A/D Converter with Sample/Hold
  • (HOLD/HLDA)’ Bus Protocol
  • OTPROM One-Time Programmable Version

N80C196KC20 Specifications

Under Biasb55°C to a125°C
Storage Temperatureb65°C to a150°C
Voltage On Any Pin to VSSb0.5V to a7.0V(1)
Voltage from EA OR
Power Dissipation1.5W(2)

N80C196KC20 Pinout

Pin Definitions

SymbolName and Function
VCCMain supply voltage (5V).
VSSDigital circuit ground (0V). There are multiple VSS pins, all of which must be connected.
VREFReference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function.
ANGNDThe output of the oscillator inverter.
VPPThe input of the oscillator inverter and of the internal clock generator.
XTAL1Timing pin for the return from the power-down circuit. This pin also supplies the programming voltage on the EPROM device.
XTAL2The output of the internal clock generator. The frequency of CLKOUT is ¹/3 the oscillator frequency.
CLKOUTReady input to lengthen external memory cycles, interfacing to slow or dynamic memory, or bus sharing. When the external memory is not being used, READY has no effect.
  RESETReset input and open drain output.
BUSWIDTHBus Hold acknowledges output indicating the release of the bus.
NMIA positive transition causes a vector through 203EH.
INSTOutput high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch.
  EA  Input for memory select (External Access). EA equal high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA equal to low causes accesses to those locations to be directed to off-chip memory. Also used to enter programming mode.
  ALE/ADVAddress Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses.
  RD  Read signal output to external memory. RD is activated only during external memory reads.
    WR/WRL  Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes.
    BHE/WRH  Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes.
READYBus Hold acknowledges output indicating release of the bus.
HSIInputs to High-Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2, and HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSOOutputs from High-Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSI.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 08-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter.
Port 18-bit quasi-bidirectional I/O port.
Port 28-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC. Pins 2.6 and 2.7 are quasi-bidirectional.
Ports 3 and 48-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups.
  HOLDBus Hold input requesting control of the bus.
  HLDABus Request output is activated when the bus controller has a pending external memory cycle.
  BREQCumulative Program Output Verification. The pin is high if all locations have been programmed correctly since entering a programming mode.
PMODEDetermines the EPROM programming mode.
  PACTA low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete.
CPVERA high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly.
  PALEA falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave).
  PROGA falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid programming data (input to slave).
PVERA high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte is programmed correctly.
  AINCAuto Increment. An active low input signal indicates that the auto-increment mode is enabled. Auto Increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write.

N80C196KC20 Datasheet

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