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Philips Electronics - NXP Integrated Circuit - IC's

SAA7201H Datasheet – Integrated MPEG2 AVG Decoder

3.3 V, integrated MPEG2 AVG Decoder

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Package QFP160 Type
SAA7201H datasheet (PDF) Preview
SAA7201H-IC

SAA7201H overview

The SAA7201H is a 3.3 V, integrated MPEG2 AVG Decoder made by Philips Electronics - NXP, supplied in a QFP160 Type package. The absolute maximum ratings table on this page lists the 5 limits from the manufacturer's datasheet that must not be exceeded. This page brings together the SAA7201H pinout and maximum ratings, with the full datasheet PDF to preview below or download.

The SAA7201 is an MPEG2 decoder which combines audio decoding and video decoding. Additionally to these basic MPEG functions it also provides means for enhanced graphics and/or on-screen display.Due to an optimized architecture for audio and video decoding, maximum capacity in the external memory and processing power from the external CPU is available for the support for graphics

Datasheet

ne5534-datasheet-1.pdf
Format PDFSize 110 KBLanguage EN
Third-party / unverified source
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SAA7201H features

  • General
  • Uses single external Synchronous DRAM (SDRAM) organized as 1M ´ 16 interfacing at 81 MHz; compatible with the SDRAM ‘lite’ or ‘PC’
  • Fast external CPU interface; 16-bit data + 8-bit address
  • Dedicated input for audio and video data in PES or ES format; data input rate: £9 Mbytes/s in byte mode;
  • £20 Mbit/s in bit serial mode; audio and/or video data can also serve as input via CPU interface
  • Single 27 MHz external clock for time base reference and internal processing; all required decoding and presentation clocks are generated internally
  • Internal system time base at 90 kHz can be synchronized via CPU port
  • Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different tasks
  • Boundary scan (JTAG) plus external SDRAM self test implemented
  • Supply voltage 3.3 V
  • Package 160 QFP.
  • CPU relation
  • 16-bit data, 8-bit address, or 16-bit multiplexed bus; Motorola and Intel mode supported
  • Support for fast DMA transfer to either internal registers or external SDRAM
  • Maximum sustained rate to the external SDRAM is 9 Mbytes/s.
  • MPEG2 system
  • Parsing of MPEG2 PES and MPEG1 packet streams
  • Double System Time Clock (STC) counters for discontinuity handling
  • Time stamps or CPU controlled audio/video synchronization
  • Support for seamless time base change (edition)
  • Processing of errors flagged by channel decoding or demux section
  • Support for retrieval of PES header and PES private data.
  • MPEG2 audio
  • Decoding of 2 channel, layer I and II MPEG audio; support for mono, stereo, intensity stereo and dual channel mode
  • Constant and variable bit rates up to 448 kbit/s
  • Audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 kHz
  • CRC error detection
  • Selectable output channel in dual channel mode
  • Independent volume control for both channels and programmable inter-channel crosstalk control through a baseband audio processing unit
  • Storage ancillary data up to 54 bytes
  • Dynamic range control at output
  • Muting possibility via external controller; automatic muting in case of errors
  • Generation of ‘beeps’ with programmable tone height, duration and amplitude
  • Serial two channel digital audio output with 16, 18, 20 or 22 bits per sample, compatible with either I2S or Japanese formats
  • Serial SPDIF audio output
  • Clock output 256 or 384 ´ fs for external D/A converter
  • Audio input buffer in external SDRAM with programmable size (default is 64 kbit)
  • Programmable processing delay compensation
  • Software controlled stop, pause, restricted skip, and restart functions.
  • MPEG2 video Decoding of MPEG2 video up to main level, main profile Nominal video input buffer size equals 2.6 Mbit for Video Main Profile and Main Level (MP@ML) Output picture format: CCIR-601 4 : 2 : 2 interlaced pictures; picture format 720 ´ 576 at 50 Hz or 720 ´ 480 at 60 Hz 3 : 2 pull-down supported with 24 and 30 Hz sequences Support of constant and variable bit rates up to 15 Mbit/s Output

SAA7201H pinout

SAA7201H pinout diagram
PinNameDescription
1MUXmultiplexed/non-multiplexed (active LOW) bus input
2CPU_TYPEIntel/Motorola (active LOW) selection input
3DMA_ACKDMA acknowledge input
4DMA_REQDMA request input and output
5DMA_DONEDMA end input
6DMA_RDYDMA ready output
7VSS1ground for pad ring
8CSchip select input
9DSdata strobe input
10ASaddress strobe input
11R/Wread/write (active LOW) input
12DTACKdata acknowledge output
13VDD1supply for pad ring
14IRQ0individually maskable interrupts
15IRQ1individually maskable interrupts
16IRQ2individually maskable interrupts
17IRQ3individually maskable interrupts
18VSS2ground for pad ring
19VSSCO1ground for core logic
20VDDCO1supply for core logic
21DATA0CPU data interface
22DATA1CPU data interface
23DATA2CPU data interface
24DATA3CPU data interface
Show all 40 pins
PinNameDescription
25VDD2supply for pad ring
26DATA4CPU data interface
27DATA5CPU data interface
28DATA6CPU data interface
29DATA7CPU data interface
30VSS3ground for pad ring
31DATA8CPU data interface
32DATA9CPU data interface
33DATA10CPU data interface
34DATA11CPU data interface
35VDD3supply for pad ring
36DATA12CPU data interface
37DATA13CPU data interface
38DATA14CPU data interface
39DATA15CPU data interface
40VSS4ground for pad ring

Absolute maximum ratings

ParameterSymbolValueUnitConditions
supply voltage (on all supply pins)VDDMin. 3.0 / Max. 3.6V
maximum voltage on all pinsVmaxMin. 0 / Max. 5.5V
total power dissipationPtotMax. tbfWTamb = 25 °C
storage temperatureTstgMin. -55 / Max. +150°C
operating ambient temperatureTambMin. 0 / Max. +70°C

SAA7201H applications

  • Digital Video Recorders (DVRs)
  • Set-Top Boxes
  • Media Players
  • Video Streaming Devices

SAA7201H datasheet PDF preview

PDF · 110 KB

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