W163 Datasheet – Spread Aware/ Zero Delay Buffer IC



Discover the W163, a state-of-the-art Spread Aware, Zero Delay Buffer that takes signal integrity and performance to new heights. With an operating voltage range of 1.8V to 3.3V and an extended industrial temperature range of -40°C to 85°C, this robust buffer is ideal for a variety of high-speed applications. Experience seamless synchronization, minimal delay variations, and unmatched reliability with the W163, revolutionizing your designs with superior accuracy.

The W163 comprises five-output zero delay buffers, incorporating a Phase-Locked Loop (PLL) that accurately replicates a time-varying signal into five identical copies. Through internal feedback, the PLL ensures that the outputs maintain precise phase alignment with the reference inputs.

Part NumberW163
FunctionSpread Aware/ Zero Delay Buffer
PackageSOIC 8 Pin
ManufacturerCypress Semiconductor
DatasheetDownload PDF AM5890S pdf

W163 Features

  • Spread Aware – designed to work with SSFTG reference signals
  • Outputs may be three-stated
  • Extra strength output drive available (-15 version)
  • Internal feedback maximized the number of outputs available in the 8-pin package

W163 Specifications

Operating Voltage3.3V±10%
Operating Range10 < fOUT < 133 MHz
Cycle-to-Cycle Jitter200 ps
Output-to-Output Skew250 ps
Device-to-Device Skew700 ps
Propagation Delay350 ps

W163 Pinout

Pin Definitions

Pin NoPin NameDescription
1REFReference Input: The output signals Q0:3 will be synchronized to this signal
unless the device is programmed to bypass the PLL
2, 3, 5, 7Q0:3Outputs: These signals will be synchronous and of equal frequency to the signal
input at pin 1.
4GNDGround Connections: Connect all grounds to the common system ground
6VDDPower Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance
8QFBFeedback Output: This output signal does not vary from signals Q0:3 in function,
but is noted as the signal used to establish the propagation delay of nearly 0.


  • Clock signal synchronization in high-speed communication systems
  • Precision timing circuits requiring minimal delay variations
  • Memory interfaces requiring enhanced signal integrity
  • Spread Spectrum Frequency Timing Generator (SSFTG) integration

W163 Datasheet

Download the W163 Datasheet from the link given below.