CD4175 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4175 has a Quad D-type flip-flop
CD4175 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.
CD4175 Features
- Complementary Outputs
- Static Operation
- All Inputs and Outputs Buffered
- Diode Protection on All Inputs
- Supply Voltage Range = 3.0 Vdc to 18 Vdc
- Output Compatible with Two Low–Power TTL Loads or One
- Low–Power Schottky TTL Load
CD4175 Specifications
Absolute Maximum Ratings
- DC Supply Voltage Range, (VDD): -0.5V to +18V
- Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
- DC Input Current, Any One Input: ±10mA
- Storage Temperature Range (TSTG): -65oC to +150oC
- Lead Temperature (During Soldering): +265oC
- At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
CD4175 Pinout Diagram
CD4175 Pin Description
| Pin No | Pin Name | Description |
| 1 | R’ | Complement Reset Pin |
| 2 | Q0 | Output Q0 Of D-Flip-Flop |
| 3 | Q0′ | Complement Output Q0′ Of D-Flip-Flop |
| 4 | D0 | Data D0 Input Pin |
| 5 | D1 | Data D1 Input Pin |
| 6 | Q1′ | Complement Output Q1′ Of D-Flip-Flop |
| 7 | Q1 | Output Q1 Of D-Flip-Flop |
| 8 | VSS | Supply Voltage |
| 9 | C | Clock Pin |
| 10 | Q2 | Output Q2 Of D-Flip-Flop |
| 11 | Q2′ | Complement Output Q2′ Of D-Flip-Flop |
| 12 | D2 | Data D2 Input Pin |
| 13 | D3 | Data D3 Input Pin |
| 14 | Q3′ | Complement Output Q3′ Of D-Flip-Flop |
| 15 | Q3 | Output Q3 Of D-Flip-Flop |
| 16 | VDD | Drain Voltage |
CD4175 Circuit
Applications
- Create delay-lines
CD4175 Alternative Equivalent
CD4174
Download CD4175-Quad D-type flip-flop Datasheet from the link given below.
